Consider the following MIPS code sequence.

add $2, $2, $2

add $5, $5, $5

L: lw $8, 1000 ($5)

sub $5, $2, $8

addi $2, $2, -4

beq $2, $0, L

sw $5, 500 ($2)

(a) Assume that there is no forwarding unit (including register file forwarding) but instead there is a data hazard detection unit that introduces the stalls needed to avoid data hazards. Suppose the processor uses Assume Branch Not Taken strategy and branches are resolved in the ID stage. Illustrate the execution of the given code.

instruction	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
add	F	D	E	M	W
add		F	D	E	M	W
lw
sub
addi
beq
sw

[Note] F: Fetch, D: Decode, E: Execution, M: Memory Access, W: Register Write Back

(b) Suppose the situation beq will be taken and branches are resolved in the ID stage (Processor uses Assume Branch Not Taken strategy). Show the execution of the given code around the loop, starting with the execution of a beq instruction and ending with the next execution of a beq.

instruction	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
add	F	D	E	M	W
add		F	D	E	M	W
lw
sub
addi
beq
sw

[Note] F: Fetch, D: Decode, E: Execution, M: Memory Access, W: Register Write Back

(c) Redraw a diagram that describes the execution of the given code assuming that the processor has a forwarding unit.

instruction	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
add	F	D	E	M	W
add		F	D	E	M	W
lw
sub
addi
beq
sw

[Note] F: Fetch, D: Decode, E: Execution, M: Memory Access, W: Register Write Back