Consider the following program:On a single cycle CPU, this program takes $26$ cycles to finish.On a multi$-$cycle CPU, this program takes $104$ cycles to finish.On a pipelined CPU, the beq instruction will cause control hazard for a total of $3$ times for the entire execution of this program.

On a pipelined CPU, control hazard will cause the sub instruction to be flushed $4$ times for the entire execution of this program.

On a pipelined CPU, there is a data hazard between ori and Iw instruction about $$8$; it can be solved using forwarding path without any delay.

On a pipelined CPU, there is a data hazard between Iw and andi instruction about $$9$; it cannot be solved without some delay.

On a pipelined CPU, there is a data hazard between sw and addi instruction about $$8.$

On a pipelined CPU, there is a data hazard between sitt and beq instruction about $$11$; it can be solved using forwarding path without any delay.

On a pipelined CPU, there is a data hazard between addi and stt instruction about $$8$; it can be solved using forwarding path without any delay.

On a pipelined CPU, there is a data hazard between andi and sw instruction about $$9$; it can be solved using the forwarding path without any delay.