Consider the following tables: a. [5 points] Assuming a pipelined processor WITHOUT forwarding, populate the following...

 

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Consider the following tables: a. [5 points] Assuming a pipelined processor WITHOUT forwarding, populate the following pipeline diagram using the compact notation. Note: Use S for stalls when needed before IF stage. Instructions add $t0,$t0,$t12 addi $10,$t0,4 lw $t2, 0($10) lw $t1, 4($12) add $t0,$t1,$t2 TO T1 T2 T3 T4 TS T6 T7 T8 T9 T10 TIL T12 T13 T14 T15 T16 T17 T18 T19 Table 1 b. [5 points] Assuming a pipelined processor WITH full forwarding, populate the following pipeline diagram using compact notation. Note: Use S for stalls when needed before IF stage. Instructions TO T1 T2 T3 T4 T5 T6 T7 TR T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 add $t0,$t0,$t2 addi $50,$t0,4 lw $t2, 0($10) lw $t1, 4($12) add $t0,$t1,$t2 Table 2 Consider the following tables: a. [5 points] Assuming a pipelined processor WITHOUT forwarding, populate the following pipeline diagram using the compact notation. Note: Use S for stalls when needed before IF stage. Instructions add $t0,$t0,$t12 addi $10,$t0,4 lw $t2, 0($10) lw $t1, 4($12) add $t0,$t1,$t2 TO T1 T2 T3 T4 TS T6 T7 T8 T9 T10 TIL T12 T13 T14 T15 T16 T17 T18 T19 Table 1 b. [5 points] Assuming a pipelined processor WITH full forwarding, populate the following pipeline diagram using compact notation. Note: Use S for stalls when needed before IF stage. Instructions TO T1 T2 T3 T4 T5 T6 T7 TR T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 add $t0,$t0,$t2 addi $50,$t0,4 lw $t2, 0($10) lw $t1, 4($12) add $t0,$t1,$t2 Table 2

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