Consider the following VHDL code and identify the syntax error$($s$)$ within it:

Select one:

a$.$ the semicolon at the last port defined in the entity must be omitted

b$.$ The MODE signal has more bits than necessary for the selection cases provided.

c$.$ The quotation marks around bit vector literals in the when clauses are incorrect.

d$.$ The syntax of the selected signal assignment statement has an extra semicolon at the

end.

e$.a+d$