Consider the following VHDL code and identify the syntax

error$($s$)$ within it:

Select one:

a$.$ The concatenation operation $\text{'}0\text{'}$ & IN$\_$A &

IN$\_$B generates a BIT$\_$VECTOR of incorrect size

for OUTPUT.

b$.$ The selected signal assignment syntax is

incorrect for VHDL$.$

c$.$ The literal $\text{'}O\text{'}$ is of type BIT, which cannot

be concatenated with BIT$\_$VECTOR types

without explicit conversion.

d$.$ The SEL signal's range is too large for the

provided selection cases.