Consider the follwing code: ADD X1, X2, #5 ADD X4, X1, #15 ADD X3, X1, X2 ADD X5, X3, X2 Assume that there is no data forwarding between instructions. A dependent instruction must wait until the previous instruction writes back data. We can assume a register can be written and read in the same cycle. So, you need to stall dependent instructions. A) Show how these instructions flow through the pipeline stages IF (instruction fetch), ID (instruction decode), EX (execute), MEM (data memory access), WB (write back results). How many cycles are needed to complete the code sequence? B) Suppose the processor handles data hazards and includes data forwarding (thus eliminating the stall). How many cycles are needed to complete the code sequence? C) However, the cycle time is increased 25% because of the extra hardware needed for data forwarding. Which processor executes the code faster? ---- Please neatly answer a, b, and c. Include all steps and as much detail as possible, I will mark as helpful.