Consider the previous assembly program.

L$.$D F$010($R$1)$

L$.$D F$120($R$2)$

ADD.D F$2$ F$0$ F$1$

MUL.D F$3$ F$0$ F$4$

BEQZ R$3$ TARGET

SUB.D F$1$ F$3$ F$4$

DIV.D F$6$ F$10$ F$0$

ADD.D F$3$ F$7$ F$8$

TARGET: SUB.D F$3$ F$2$ F$2$

S$.$D F$320($R$2)$

ADD.D F$1$ F$5$ F$3$

Consider a processor performing dynamic scheduling with Tomasulo$$s algorithm and Reorder Buffer.

$$ The processor has the following $($unpipelined$)$ execution units: $1$ Integer Unit $($latency: $1$ clock cycle$),2$ FP

Adders $($latency: $2$ clock cycles$),1$ FP Divider $($latency: $20$ clock cycles$),1$ FP Multiplier $($latency: $10$ clock

cycles$)$ and $1$ Memory Unit $($latency: $10$ clock cycle including address computation and memory access$).$

$$ The processor has three sets of reservation stations: one shared by the adders and the integer unit $(3$ Addx$),$

one for the memory $(2$ Loadx$),$ and one shared by multiplier and divider $(2$ Multx$).$

$$ The ROB has $6$ entries.

Assume that branch target and condition are computed by the Integer Unit. In the presence of a branch, the processor

will by default take the fall$-$through path.

Assume R$1=10,$ R$2=20,$ Mem$[20]=10,$ Mem$[40]=30$

Use the tables provided in the next pages to walk through the execution of the code in the following four situations:

a$.$ One$-$issue processor, Tomasulo $+$ ROB, R$3=10$

b$.$ One$-$issue processor, Tomasulo $+$ ROB, R$3=0$

c$.$ Four$-$issue processor, Tomasulo $+$ ROB, R$3=0$

In all cases, the reservation stations and reorder buffer tables are provided at the end for your convenience. You do

not need to fill these tables $($however$,$ you need to know what they are for$).$ You are required only to fill:

$-$ The table indicating the progress of the instruction, cycle by cycle. In this table you should also indicate the

tag of the reservation station and the ROB entry used by the instruction.

$-$ The final value of the registers.

When flushing the ROB, please strike out the instructions $($and do not delete them from the table$).$

In filling the tables, please assume that:

$-$ If an instruction I is using a ROB entry, such ROB entry becomes available and can be used in the clock

cycle after I commits.

$-$ If an instruction I uses a reservation station or an execution unit, such reservation station$/$execution unit is

freed when I writes the result, and is available to a different instruction starting from the next clock cycle.

Question $1$: Why don$$t we need to wait until I is completely done?

$-$ If an instruction J depends on instruction I, the data written by instruction I will be available to J in the clock

cycle when I writes the result $($say t$),$ and $($in the absence of data hazard$),$ instruction J will be able to execute

in the following clock cycle $($say t$+1).$

Question $2$: In the presence of a ROB, why don$$t we need to wait

until I commits?

$-$ If the branch is mispredicted, the target instruction of the branch is fetched in the clock cycle after the branch

instruction commits.

Question $3$: The presence of the ROB and of the commit stage allows handling exceptions in a dynamically scheduled

processor. Why?

Provide a clear but concise answer to the $3$ questions and fill in the table for cases:

TOMASULO W$/$ ROB, ONE$-$ISSUE PROCESSOR, R$3=10$

TOMASULO W$/$ ROB, ONE$-$ISSUE PROCESSOR, R$3=0$

TOMASULO W$/$ ROB, FOUR$-$ISSUE PROCESSOR, R$3=0$