Consider the reservation table in Figure 8.4. Suppose that the processor includes forwarding logic that is able to tell that instruction A is writing to the same register that instruction B is reading from, and that therefore the result written by A can be forwarded directly to the ALU before the write is done. Assume the forwarding logic itself takes no time. Give the revised reservation table. How many cycles are lost to the pipeline bubble?

 

hardware resources: instruction memory A BCDE register bank read 1 A BCDE register bank read 2 A BCDE ALU BCDE BCDE BCDE A data memory A register bank write A 1 2 3 4 5 6 7 8 9 10 11 12 cle interlock