Consider the same code as question $7.$ This time, assume a processor with a

Tomasulo organization. This processor has a separate LOAD$/$STORE unit, which is capable of

executing one load or store operation at a time. Load latency is $1$ cycle. It also has an integer

unit, two Floating point add$/$sub units, and a floating point multiply unit; latencies of these

units are the same as in problem $7.$ Assume that any number of instructions can be issued in

a given clock cycle, and that instructions can execute in the next clock cycle after a value is

produced by another functional unit.

In the tables below, show the status of the processor just as the SD has issued, and determine

the Clock Cycle when this occurs. When updating the scoreboard, when the status changes,

cross out the previous state, and then write in the new state $($i$.$e$.,$ don$$t erase the previous

history; cross it out$).$