Consider the small logic network shown below. There are $3$ primary inputs $($PIs$)$ labeled: A$,$ B$,$ C$.$ There is $1$ primary output $($PO$)$: Z$.$ There are $4$ logic gates. There are $3$ internal wires that represent gate outputs$/$inputs$,$ labeled: w$1,$ w$2$ and w$3.$ The gate delay $($cell arc$)$ for each inverter is $2.$ The gate delay for each NAND$2$ is $3.$ Ignore delay for the wires. This logic operates on a clock with a Cycle Time $=7.$

Do the following:

Build the Delay Graph for this logic network, including one source $($SRC$)$ and one sink $($SNK$)$ node, and appropriate edges representing all the delays.

Walking this graph from SRC to SNK$,$ calculate the Arrival Time $($AT$)$ for each node in this graph. Just use your eyes to determine the necessary longest paths.

Walking this graph from SNK to SRC$,$ calculate the Required Arrival Time $($RAT$)$ for each node in this graph. Again, just use your eyes to determine the necessary longest paths.

Using these computed ATs and RATs, compute the Slack value for each node in this graph.

Which of the following are correct statements of the results of this Static Timing Analysis:

$15$ points

After the static timing analysis, node SRC is labeled with AT$=0,$ RAT$=-2,$ Slack$=-2.$

The delay graph has $11$ edges in total.

After the static timing analysis, node C is labeled with AT$=0,$ RAT$=-2,$ Slack$=-2.$