Consider the Verilog code below. Determine the function of this circuit. Rewrite the codeusing case statement, with z$[$i$]$ declared as a vector.module prob$1($A$,$ en$,$ z$0,$ z$1,$ z$2,$ z$3)$;input $[1$:$0]$ A;input en;output z$0,$ z$1,$ z$2,$ z$3$;reg z$0,$ z$1,$ z$2,$ z$3$;always @ $($A or en$)$beginz$0=0$;z$1=0$;z$2=0$;z$3=0$;if $($en$)$if $($A $==0)$z$0=1$;else if $($A $==1)$z$1=1$;else if $($A $==2)$z$2=1$;elsez$3=1$;endendmodule