Consider the VHDL code based on the last digit of your student number. At t=0ns, the signals A, B, C and D are initialized to zero and the process and concurrent statements get executed. Simulate up to 23ns and specify the time, delta () time and the values of A, B, C and D each time a change occurs.

begin

P1:process(B)

begin A <= 1; A <= transport 0 after 4 ns;

end process P1;

D <= A or B after 4 ns;

P2:process(A)

begin

if A = 1 then B <= not B after 11 ns;

end if; C <= not B;

end process P2;

end test1