Consider two design alternatives $($Design A and Design B$)$ for a superscalar machine. Assume that Design A is a dynamically dispatched, statically scheduled machine that allows up to four integer instructions to be executed and retired in $1$ cycle but that all floating point instructions are executed serially with a fixed $100$ cycle delay. Assume that design B is a dynamically dispatched, dynamically scheduled machine that dispatches up to $2$ instructions per cycle and with $4$ integer execute units and $1$ floating point execute unit. Assume that the execute units can process at most one instruction per execution period and that the execution period of integer operations is $3$ cycles and floating point operations is $200$ cycles. What is the relative performance of these two designs? You can ignore the performance impact of data hazards for both design solutions.