Consider two implementations of a $6-$input OR gate:

Design A:

Consists of two $3-$input domino OR gates, followed by a $2-$input domino OR gate.

Inverters in domino stages are high$-$skewed, with PMOS transistors being $4$ times wider than NMOS.

Design B:

Consists of a two dynamic $3-$input NOR gates,

Followed by a $2-$input high$-$skewed static NAND gate$($such that PMOS transistors are two times wider than NMOS$).$ what is the logical effort for design A and B $?$