Consider two pipelined processors. Suppose data references represent $40\%$ of the instructions executed and that the ideal CPI of the pipelined processor $($no structural hazard$)$ is $1.$

$(10$ points$)$ Suppose in Processor A$,$ data references represent $40\%$ of the instructions executed and that the ideal CPI of the pipelined processor $($no structural hazard$)$ is $1.$ Assume that the processor A with the hazard has a clock rate that is $1\mathrm{.}05$ times higher than the hazard free processor and incurs a one cycle stall on structural hazards as in our example. Is the pipeline with or without the structural hazard faster, and by how much?