Consider two SRAMs. One is $256$K x $4$ and has a tRC of $16$ ns$.$ The other is $128$K x $8$ and has a tRC of

$20$ns$.$

a$.[5]$ What are the effective bandwidths of the two devices?

b$.[5]$ Now, consider that the devices are to be used to provide data to a $32-$bit bus. What is the data

rate that can be sustained on the bus if it is driven by $8$ of the $256$Kx$4$ chips in parallel?

c$.[5]$ What is the corresponding bus data rate if four of the $128$K x $8$ SRAMs are used in parallel?

d$.[5]$ Ignoring control, power, and ground pins, discuss the trade$-$offs in pin count between a $16$Mb

SRAM organized as a x$8$ device or as a x$32$ device. Assume data pins are bidirectional.

e$.[5]$ Assume you have an embedded system that requires a new byte of memory data every $5$ns$.$

How might you use $128$K x $8$ SRAM chips to achieve this?