Considering ARMv$8$ memory system, select the three incorrect statements:

All other answers are incorrect.

There are separate Level $1$ TLBs for instructions and data

Both instructions and data use the same cache memory.

There are separate Level $2$ TLBs for instructions and data

"Cache miss" is when the requested item $($instruction or data$)$ is not found in the corresponding cache.

Each core has dedicated Level $2$ cache memory

Level $2$ cache is mostly used by the GPU rather than CPU