Convert it to JK flip-flop by adding the necessary

decoding logic. Merge the decoding logic with the logic gates of the SR flip-flop.

Initially, the flip-flop is at a reset state with J and K at zero. When the clock goes high,

J and K are simultaneously brought to logic “1” for a period ten times longer than the propagation delay of a logic gate. Show the effects of this on the Q and Q’ outputs with the aid of a timing diagram. Assume that all the gates in the circuit have the same propagation delay.

 

Transcribed Image Text:

J CLK K 1 I 1 0 t 0 ta 2ta 3td Ata 5ta 6ta 7td 0 0 0 Set Set Reset 0 0 1 0 1 0 0 0 1 0 →1 Reset 0 1 1 0 0 Q 0 0 0 1 1 0 0 0 1 Q 1 1 0 0 0 0 1 1 0 lo Q NOR function AB Y 0 0 1 01 0 10 0 11 0 J CLK K 1 I 1 0 t 0 ta 2ta 3td Ata 5ta 6ta 7td 0 0 0 Set Set Reset 0 0 1 0 1 0 0 0 1 0 →1 Reset 0 1 1 0 0 Q 0 0 0 1 1 0 0 0 1 Q 1 1 0 0 0 0 1 1 0 lo Q NOR function AB Y 0 0 1 01 0 10 0 11 0

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