Question: (!(count > 1 && count < 19)) VERILOG CODE syntax IN FPGA Can someoone explain what the '!'(exclamation point) means and write this line if

(!(count > 1 && count < 19))

VERILOG CODE syntax IN FPGA

Can someoone explain what the '!'(exclamation point) means and write this line if VHDL code syntax

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