Counters Experiment A counter is a sequential circuit which goes through a sequence of states upon the application of a clock, and input signals. Its state diagram contains a single cycle. Counters may be classified as synchronous or asynchronous (ripple counter), and by its modulus, which is the number of states in its cycle. Sequential Logic Circuit Design Procedure (synchronous) 1. From the information given in the problem statement create a state diagram, then a state output table. You may start directly with the state output table, by eliminating the state diagram step, but I caution you that with some problems it is easier to visualize the sequential states sequence through the use of a state diagram. 2. Minimize the number of states in the state output table by eliminating equivalent states. Two states are equivalent if they produce the same output and their next states are the same. 3. Derive a transition output table by substituting each state from the state output table with a set of state variables whose values uniquely identify each state. 4. Determine the type of flip-flop to be used in the design, then construct their excitation table. These table show which input values are needed by the flip-flop to reach the desired next state for each state input combination. 5. Derive the flip-flop's input excitation function, from the excitation table. 6. Derive the output equation(s) from the transition output table. 7. Draw the logic diagram. Experiment: A - Design and build an up/down synchronous 2-bit counter with an enable and with the following count sequence: 0,1,2,3,0, ... or 3, 2, 1,0,3