Create $4$ bit computation units $($CUs$,$ purple$)$ capable of computing these $4$

logic operations: AND, NOR, NAND, XOR. For the first row of the design,

the data inputs will be provided externally, written to their corresponding

storage units, then read from their storage units to their corresponding CU

data input ports. After the CU computes the results, the data must be

written to its output data storage unit. The output data will be used as both

inputs for the CU input data storage units in the next row. The final outputs

$($in an array$)$ should be from the CUs in the final row only.Each row can do the storage operations of all the columns in parallel, you

do not need to do column by column. It is required to use arrays for all of

the ports and signals. Write a vhdl code with test cases for this.