Create a block diagram, truth table, kmap and logic circuit from the following VHDL code.

eei USE ieee std logic 1164 alli ENTITY R IS GENERIC ( N : INTEGER := 8 ) PORT x IN STD_LOGIC_VECTOR (N-1 DOWNTO 0) IN STD LOGIC FoUT STD_LOGIC _VECTOR (N-1 DOWNTO 0) ARCHITECTURE Behavior OF BEGIN IS F 'Z') WHEN E = 'O' ELSE X END Behaviori eei USE ieee std logic 1164 alli ENTITY R IS GENERIC ( N : INTEGER := 8 ) PORT x IN STD_LOGIC_VECTOR (N-1 DOWNTO 0) IN STD LOGIC FoUT STD_LOGIC _VECTOR (N-1 DOWNTO 0) ARCHITECTURE Behavior OF BEGIN IS F 'Z') WHEN E = 'O' ELSE X END Behaviori