Create a FIFO module based on the symbol and description below:

Your FIFO$$s data width and depth should be parameterized, for the test cases, use width $8$ and depth $32.$

You would use the same clock for read and write

provide empty$/$full and almost empty$/$ almost full flags, for the almost flags make it a parameter, for the

test case use $2.$

You should use read$/$write counter to keep track of data locations, provide count of the FIFO as an

output, this is different than write$/$read counters.

Provide a valid signal on successful read

Provide overflow$/$underflow flags

Design can$$t be empty and full at the same time, same with similar flags