Create a testbench in VHDL where you can read stimulus vectors from a file and write the output vectors to a file. Create a simple component to test (such as adding 1 to the input). Upload four files to D2L 1. The stimulus file that contains input numbers 2. The output file that shows that the numbers in the input file have increases by one 3. The add1 component VHDL code. 4. The VHDL testbench code that reads the stimulus file, drives the add1 component, and writes the result to a file. Create a testbench in VHDL where you can read stimulus vectors from a file and write the output vectors to a file. Create a simple component to test (such as adding 1 to the input). Upload four files to D2L 1. The stimulus file that contains input numbers 2. The output file that shows that the numbers in the input file have increases by one 3. The add1 component VHDL code. 4. The VHDL testbench code that reads the stimulus file, drives the add1 component, and writes the result to a file