Create a UVM model consisting of a sequence, sequencer, and driver $($Contained in some hierarchy of your choice$).$ Generate $50$ patterns to test the carry from bit $15$ to bit $16$ in an ALU. Generate $100$ patterns to test bit XOR for all $36$ bits. Print the pattern data in the driver $($There is no DUT for this problem$).$

Assume the ALU has $4$ inputs

A $39$ bits signed

B $22$ bits signed

op $1$ bit $0=$ add $1=$xor

ci $1$ bit $($carry in$)$

Assume the ALU has $2$ outputs

Z $36$ bits signed

co $1$ bit $($carry out$)$