CS$4210$

In$\_$Class$\_$Assignment $1(50$ marks$)$

Draw the logic diagram of the circuit described by the following Verilog HDL $(20$ marks$),$

simulate it $(10$ marks$),$ and answer what operation it implemented $(20$ marks$)?$

ing the simulation outputs$)$ to Moodle.

module Circuit$\_$o $(A,B,C,F1,F2)$; put $A,B,C$

input $A,B,C$; output $F1,F2$;

wire $T1,T2,T3,F{2}_b,E1,E2,E3$;

or $G_1(T1,A,B,C)$;

and $G2(T2,A,B,C)$;

and $G_3(E1,A,B)$;

and $G_4(E2,A,C)$;

and $G5(E3,B,C)$;

or $,G6(F2,E1,E2,E3)$;

not $G7($F$2\_$b$,$ F$2)$;

and $G8(T3,T1,F{2}_b)$;

or $G9(F1,T2,T3)$;

endmodule

$//$ Stimulus to analyze the circuit

module test$\_$circuit;

reg$[2$:$0]D$;

wire $F1,F2$;

Circuit$\_$o UUT $($D$[2],$ D$[1],$ D$[0],$ F$1,$ F$2)$; $//$ Instantlate UUT

initial

begin $//$ Apply stimulus

$D=3^{\text{'}}b000$;