Question: CSC 3 6 2 Homework Assignment # 7 Due Date: Wednesday, April 2 4 Word Processor all answers, show work for partial credit. 1 )

CSC 362 Homework Assignment #7
Due Date: Wednesday, April 24
Word Processor all answers, show work for partial credit.
1) Architectures are considering one of two changes to their processor. The first is to increase
the L1 cache hit time from .5 ns to .3 ns per cycle. The processor operates while there are
no stalls in the pipeline. With this increase, they anticipate an average of .6 stalls per
instruction. The second is to increase the TLBs size. Currently, the TLB has a miss rate of
15% but the increased size will change this to only 6%. When the TLB misses, the page
table in DRAM must be accessed. DRAM access is 20 ns (recall from above, the L1 cache,
which includes the TLB, can be accessed in .5 ns). Use Amdahls Law to compute the
speedup of both options and state which should be implemented.
2) Answer the following questions about the 4 forms of I/O.
a. Assume an input task requires moving 1024 bytes from input to memory. Further,
assume that each transfer is 1 byte at a time. Assume no errors occur.
i. If this task was handled by programmed I/O, how many interrupts would take
place?
ii. If this task was handled by interrupt-driven I/O, how many interrupts would
take place?
iii. If this task was handled by DMA I/O, how many interrupts would take place?
iv. If this task was handled by channel I/O, how many interrupts would take place?
b. What additional hardware will a DMA controller have over an I/O module that uses
interrupt-driven I/O?
3) Use the figure on slide 11 to answer the following questions.
a. What are the D1D0 lines used for?
b. In our computers, we do not use these two lines, what do we use in place of them
and why?
c. Why should the keyboard have a higher priority over the disk drive to interrupt the
CPU?
4) Assume we have six drives in a RAID configuration whereby a parity byte is stored using
five data bytes and stored on the sixth drive. We have the following values where the byte
on disk 4 is inaccessible. What is this missing byte? (restore it by using the other seven
bytes, assume even parity is used)
Disk 1: 11101111
Disk 2: 10101110
Disk 3: 10101110
Disk 4: ------------
Disk 5: 00100100
Parity: 01100010
5) Answer the following regarding RAID levels.
a. How does RAID 5 improve over RAID 4?
b. How does RAID 6 improve over RAID 5?
c. RAID 0 uses no redundancy so why would anyone select RAID 0 at the added
expense of using RAID?
d. Although RAID 3 would provide a better performance over RAID 5, RAID 3 is
seldom used, why?
6) Answer the following questions regarding using a binary semaphore to implement
synchronization.
a. Show how the wait and release functions are implemented.
b. Why is the while loop in wait not an infinite loop?
c. What would happen if we initialize the semaphore to 2 instead of 1?
d. We implement wait and release using atomic instructions. What is an atomic
instruction and why should we use one to implement these functions?
7) Given the C program below, provide the run-time stack as it would appear at point P1. For
each variable/parameter on the stack, list it as well as its current value. You will have to
work through the logic of the code to determine the order that functions are called.
void main(){
int x =3;
foo(x);
}
void foo(int a){
int b =1;
printf(%d
, bar(a)+b);
}
int bar(int z){
if(z>0) return bar(z-1)+1;
else return dummy();
}
int dummy(){
int c =1; P1
return c;

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