CSC601 Computer Organization and Architecture Assignment 1 (10%) Due Date: 11^th March 2023 Submit to: timothy.kale@sinu.edu.sb Answer the following questions below; Lecture 4 Readings, Chapter 5 Question 1: Suggest reasons why RAMs traditionally have been organized as only one bit per chip whereas ROMs are usually organized with multiple bits per chip. Question 2: Consider a dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns; a memory cycle requires 250 ns. What percentage of the memorys total operating time must be given to refreshes? Question 3: The memory of a particular microcomputer is built from 64K x 1 DRAMs. According to the data sheet, the cell array of the DRAM is organized into 256 rows. Each row must be refreshed at least once every 4 ms. Suppose we refresh the memory on a strictly periodic basis.

1. What is the time period between successive refresh requests?
2. How long a refresh address counter do we need?

Question 4: Suppose an 8-bit data word stored in memory is 11000010. Using the Hamming algorithm, determine what check bits would be stored in memory with the data word. Show how you got your answer. Lecture 4 Readings, Chapter 6 Question 5: Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 kB. The average seek time is 8 ms, the track-to-track access time is 1.5 ms, and the drive rotates at 3600 rpm. Successive tracks in a cylinder can be read without head movement.

1. What is the disk capacity?
2. What is the average access time? Assume this file is stored in successive sectors and tracks of successive cylinders, starting at sector 0, track 0, of cylinder i.
3. Estimate the time required to transfer a 5-MB file.
4. What is the burst transfer rate?

Question 6: Consider a disk that rotates at 3600 rpm. The seek time to move the head between adjacent tracks is 2 ms. There are 32 sectors per track, which are stored in linear order from sector 0 through sector 31. The head sees the sectors in ascending order. Assume the read/write head is positioned at the start of sector 1 on track 8. There is a main memory buffer large enough to hold an entire track. Data is transferred between disk locations by reading from the source track into the main memory buffer and then writing the data from the buffer to the target track.

1. How long will it take to transfer sector 1 on track 8 to sector 1 on track 9?
2. How long will it take to transfer all the sectors of track 8 to the corresponding sectors of track 9?

Question 7: Design a backup strategy for a computer system. One option is to use plug-in external disks, which cost $150 for each 500 GB drive. Another option is to buy a tape drive for $2500, and 400 GB tapes for $50 apiece. (These were realistic prices in 2008.) A typical backup strategy is to have two sets of backup media onsite, with backups alternately written on them so in case the system fails while making a backup, the previous version is still intact. Theres also a third set kept offsite, with the offsite set periodically swapped with an on-site set.

1. Assume you have 1 TB (1000 GB) of data to back up. How much would a disk backup system cost?
2. How much would a tape backup system cost for 1 TB?
3. How large would each backup have to be in order for a tape strategy to be less expensive?
4. What kind of backup strategy favors tapes?

Lecture 5 Readings, Chapter 7, 8 Question 8: On a typical microprocessor, a distinct I/O address is used to refer to the I/O data registers and a distinct address for the control and status registers in an I/O controller for a given device. Such registers are referred to as ports. In the Intel 8088, two I/O instruction formats are used. In one format, the 8-bit opcode specifies an I/O operation; this is followed by an 8-bit port address. Other I/O opcodes imply that the port address is in the 16-bit DX register. How many ports can the 8088 address in each I/O addressing mode? Explain your answer. Question 9: A microprocessor scans the status of an output I/O device every 20 ms. This is accomplished by means of a timer alerting the processor every 20 ms. The interface of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device, given a clocking rate of 8 MHz? Assume for simplicity that all pertinent instruction cycles take 12 clock cycles. Question 10: In virtually all systems that include DMA modules, DMA to main memory is given higher priority than CPU access to main memory. Why? Question 11: Consider a fixed partitioning scheme with equal-size partitions of 216 bytes and a total main memory size of 224 bytes. A process table is maintained that includes a pointer to a partition for each resident process. How many bits are required for the pointer? Question 12: Give reasons that the page size in a virtual memory system should be neither very small nor very large. Lecture 6 Readings, Chapter 9, 10, 11 Question 13: Convert the following binary numbers to their decimal equivalents:

	001100
	000011
	011100
	111100
	101010

Question 14: Convert the following decimal numbers to their binary equivalents:

	64
	100
	111
	145
	255

Question 15: Represent the following decimal numbers in both binary sign/magnitude and twos complement using 16 bits: + 512; - 29. Question 16: Assume numbers are represented in 8-bit twos complement representation. Show the calculation of the following:

1. 6 + 13
2. -6 + 13
3. 6 - 13
4. -6 13

Question 17: Construct a truth table for the following Boolean expressions:

1. ABC +
2. ABC + +
3. A ( + )
4. (A + B)(A + C)( )

Attachments:

CSC601-Assign....pdf