CSCI 223 Computer Org. & Assembly Language Homework #7 DUE: 5/1/2018 (Tuesday), 9:30 AM Submission: Submit the hard copy of your homework in class (after printing if electronically written) Simulate a small virtual memory system with TLB and L1 D-cache with following assumptions .The memory is byte addressable .Memory accesses are to 1-byte words (not 4-byte words) Virtual addresses are 14 bits wide (n-14) Physical addresses are 12 bits wide (m - 12) The page size is 64 bytes (P 64) .The TLB is four-way set associative with 16 total entries The L1 D-cache is physically addressed and direct-mapped, with a 4-byte line size and 16 total sets Figure below shows the format of the virtual and physical addresses. Since each page is 26-64 bytes, the low-order 6 bits of the virtual and physical addresses serve as the VPO and PPO respectively. The high-order 8 bits of the virtual address serve as the VPN. The high-order 6 bits of the physical address serve as the PPN 13 1210 9 87 65 43 21 0 address Virtual page number) (Virtual page offset) 10 9 8 76 543 20 (Physical page number) (Physical page offset) Figure below shows a snapshot of our little memory system including the TLB (a), a portion of the page table (b), and the L1 cache (c). Above the figures of the TLB and cache, we have also shown how the bits of the virtual and physical addresses are partitioned by the hardware as it accesses these devices. 13 12 11 10 9 76 5 3 2 0 Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Vali (a) TLB: Four sets, 16 entries, four-way set ssociative 07 03 2D 04 0 03 07 03 OD 0A 34 VPN PPN Valid VPN PPN Valid 08 13 01 02 03 OA OB oC 05 06 07 OE (b) Page table: Only the first 16 PTEs are shown