Description: Create a project with behavioral VHDL and evaluate the behav$-$

ioral$-$to$-$hardware translation process.

Part A: Use Vivado to create a project. Add the VHDL code which implements the multiplier

FSMD from the lecture. Open 'elaborated design' and identify components of the schematic that

correspond to elements of the VHDL code. Please include your name and the title "Lab #$5$: Mul$-$

tiplier FSMD from Lecture".

Part B: Use Vivado to create a project. Write your own VHDL code which instantiates the multi$-$

plier FSMD from Part A and implements the following:

Idle: It checks the ready signal, if $\text{'}1\text{'},$ it applies two $8$ bit values of your choice to the $8$ bit

inputs of the multiplier and asserts the start signal and transitions to the WaitMultDone state.

WaitMultDone: It continuously checks the status of the ready signal. If ready becomes $\text{'}1\text{'}$

again, it transitions back to Idle. Please title "Lab #$5$: Multiplier FSMD with Parent Module".

This lab is worth $20$ points.

$```$

FSMD Design Examples

architecture two$\_$seg$\_$arch of seq$\_$mult is

constant WIDTH: integer :$=8$;

type state$\_$type is $($idle$,$ ab$0,$ load, op$)$ ;

signal state$\_$reg, state$\_$next: state$\_$type;

signal a$\_$reg, a$\_$next: unsigned$($WIDTH$-1$ downto $0)$;

signal n$\_$reg, n$\_$next: unsigned$($WIDTH$-1$ downto $0)$;

signal r$\_$reg, r$\_$next: unsigned$(2*$WIDTH$-1$ downto $0)$;

begin

$--$ state and data register

process$($clk$,$ reset$)$

begin

if $($reset $=\text{'}1\text{'})$ then

state$\_$reg idle;

a$\_$reg others $=>\text{'}0\text{'})$;

n$\_$reg others $=>\text{'}0\text{'})$;

r$\_$reg others $=>\text{'}0\text{'})$;

$``````$

$\backslash$text $\{1$ wo Segment VHDL Descriptions of FSNIDS$\}$

elsif $($clk$\text{'}$event and clk $=\text{'}1\text{'})$ then

state$\_$reg state$\_$next;

a$\_$reg a$\_$next;

n$\_$reg n$\_$next;

r$\_$reg r$\_$next;

end if;

end process;

$--$ combinational circuit

process$($start$,$ state$\_$reg, a$\_$reg, n$\_$reg, r$\_$reg, a$\_$in$,$

b$\_$in$,$ n$\_$next$)$

begin

state$\_$next state$\_$reg;

a$\_$next a$\_$reg;

n$\_$next n$\_$reg;

r$\_$next r$\_$reg;

ready ;

$```$ Two Segment VHDL Descriptions of FSMDs

$```$

case state$\_$reg is

when idle $=>$

if $($start $=\text{'}1\text{'})$ then

if $($a$\_$in $="00000000"$ or

b$\_$in $="00000000")$ then

state$\_$next ab$0$;

else

state$\_$next load;

end if;

end if;

ready ;

when ab$0=>$

a$\_$next unsigned$($a$\_$in$)$;

n$\_$next unsigned$($b$\_$in$)$;

r$\_$next others $=>\text{'}0\text{'})$;

state$\_$next idle;

$``````$

when load $=>$

a$\_$next unsigned$($a$\_$in$)$;

n$\_$next unsigned$($b$\_$in$)$;

r$\_$next others $=>\text{'}0\text{'})$;

state$\_$next op;

when op $=>$

n$\_$next n$\_$reg $-1$;

r$\_$next & a$\_$reg$)+$ r$\_$reg;

if $($n$\_$next $="00000000")$ then

state$\_$next idle;

end if;

end case;

end process;

r std$\_$logic$\_$vector$($r$\_$reg$)$;

end two$\_$seg$\_$arch;

$```$