Description
Instructions
Timed Test	This test has a time limit of 2 hours.This test will save and submit automatically when the time expires. Warnings appear when half the time, 5 minutes, 1 minute, and 30 seconds remain.
Multiple Attempts	Not allowed. This test can only be taken once.
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Remaining Time:

1 hour, 50 minutes, 58 seconds.

Question Completion Status:

QUESTION 1

What is the decimal value of this 16-bit twos complement number?

	a.	-4
	b.	12
	c.	-12
	d.	65532

3.34 points

QUESTION 2

What is the 8-bit twos complement representation binary value of the decimal number -2?

	a.	10000010
	b.	11111110
	c.	00000010
	d.	01111101

3.34 points

QUESTION 3

The addressing mode of the following MIPS instruction (Addi $t1,$t2, 2) is

	a.	Register addressing mode
	b.	Base displacement addressing mode
	c.	Immediate addressing mode
	d.	PC-relative addressing mode

3.34 points

QUESTION 4

The following MIPS AND instruction (and $t1,$t2,$t3) will

	a.	Perform $t1 and $t2 and store the result into $t3
	b.	Perform $t1 and $t3 and store the result into $t2
	c.	Perform $t2 and $t3 and store the result into $t1
	d.	Perform $t3 and $t1 and store the result into $t2

3.34 points

QUESTION 5

If $t1 = 11, $t2 = 10 and $t3 = 01, what are the final values of these registers after executing the previous MIPS instruction

	a.	$t1=00 , $t2=10 , and $t3= 01
	b.	$t1=11 , $t2=00 , and $t3= 10
	c.	$t1=01 , $t2= 11 , and $t3=00
	d.	$t1=01 , $t2= 10 , and $t3= 01

3.34 points

QUESTION 6

What is 5ED4-07A4 when these values represent unsigned 16-bit hexadecimal numbers? The result is in Hexadecimal.

	a.	5730
	b.	5EA8
	c.	5780
	d.	0000

3.34 points

QUESTION 7

The following instructions executed by a pipelined processor without forwarding unit. What type of hazard is there?

Add $t0, $s0, $s1

Sub $s2, $t0, $t3

	a.	Structural
	b.	Control
	c.	Structural and Data
	d.	Data

3.34 points

QUESTION 8

In the same instructions mentioned above, what is the minimum number of stall cycles that are needed to solve this hazard without using a forwarding unit?

	a.	3
	b.	1
	c.	0
	d.	2

3.34 points

QUESTION 9

With a forwarding unit, what is the minimum number of stall cycles that are needed to solve this hazard for the same instructions given above?

	a.	0
	b.	1
	c.	2
	d.	3

3.34 points

QUESTION 10

For the following MIPS instruction, what is the minimum number of stall cycles that are needed to solve this hazard with forwarding unit?

LW $t0, 0($t2)

Sub $s2, $t0, $t3

	a.	0
	b.	1
	c.	2
	d.	3

3.34 points

QUESTION 11

Branch prediction is a method to solve a pipelining hazard. What kind of hazard this method can be used?

	a.	Structural
	b.	Control
	c.	Structural and Data
	d.	Data

3.33 points

QUESTION 12

Assume the individual stages of the datapath have the following latencies:

IF: 250 ps

ID: 350 ps

EX: 150 ps

MEM: 300 ps

WB: 200 ps

Assume the instructions executed by the processor are broken down as follows:

ALU: 45%

Beq: 20%

LW: 20%

SW: 15%

What is the clock cycle time in a pipelined and non-pipelined processor?

	a.	Pipelinied: 150ps, Non-pipelined: 1250ps
	b.	Pipelinied: 350ps, Non-pipelined: 1250ps
	c.	Pipelinied: 300ps, Non-pipelined: 300ps
	d.	Pipelinied: 150ps, Non-pipelined: 150ps

3.33 points

QUESTION 13

For the following instructions, what is the minimum stall cycles that are needed after the beq instruction?

Beq r5,r4,label

Add r5,r1,r4

	a.	0
	b.	1
	c.	2
	d.	3

3.33 points

QUESTION 14

Suppose that in 1000 memory references there are 40 times misses in the first level cache and 20 misses in the second level cache. What are the various miss rates?

	a.	L1 cache miss rate = 4% and L2 miss rate = 50%
	b.	L1 cache miss rate = 0.4% and L2 miss rate = 60%
	c.	L1 cache miss rate = 4% and L2 miss rate = 60%
	d.	L1 cache miss rate = 4% and L2 miss rate = 2%

3.33 points

QUESTION 15

Consider information in question 14 above, assume the miss penalty from L2 cache to the main memory is 200 cycles, the hit time to L2 cache is 10 clock cycles, the hit time of L1 is 1 clock cycle, and there are 1.5 memory references per instruction. What is the average memory access time AMAT?

Given, AMAT = Hit time L1 + Miss rate L1 x (Hit time L2 + Miss rate L2 x Miss penalty L2)

	a.	1.56
	b.	5.4 Clock Cycles
	c.	2.6
	d.	6.2

3.33 points

QUESTION 16

For two variables, n=2 , the number of possible Boolean functions is

	a.	4
	b.	8
	c.	16
	d.	12

3.33 points

QUESTION 17

The simplest way to determine cache locations in which to store memory blocks is the,

	a.	Associative Mapping technique
	b.	Direct Mapping technique
	c.	Set-Associative Mapping technique
	d.	Indirect Mapping technique

3.33 points

QUESTION 18

The sum of -6 and -13 using 2s complement addition is,

	a.	11100011
	b.	11110011
	c.	11001100
	d.	11101101

3.33 points

QUESTION 19

Which one of the following CPU registers holds the address of the instructions (instructions in the program stored in memory) to be executed next?

	a.	MAR (Memory address register)
	b.	AC (Accumulator)
	c.	PC (Program Counter)
	d.	IR (Instruction Register)

3.33 points

QUESTION 20

What are the major components of a CPU?

	a.	Control Unit, Register Set, Arithmetic Logic Unit
	b.	Register Set, Control Unit, Auxiliary Memory
	c.	Memory Unit, Arithmetic Logic Unit, Auxiliary Memory
	d.	Register Set, Control Unit, Memory Unit

3.33 points

QUESTION 21

__________ is the memory usually written by the manufacturer.

	a.	RAM
	b.	ROM
	c.	DRAM
	d.	SRAM

3.33 points

QUESTION 22

A page frame is also called as ________________.

	a.	Print document
	b.	Block
	c.	Disk
	d.	Hit

3.33 points

QUESTION 23

The performance of the cache memory is measured in terms of a quantity called _________________

	a.	Initialization Ratio
	b.	Address Ratio
	c.	Hit Ratio
	d.	Miss Ratio

3.33 points

QUESTION 24

Mean Time Between Failures MTBF, Mean Time To Replacement MTTR, and Mean Time to Failure are useful metrics for evaluating the reliability and availability of storage sources. Given the following calculate the MTBF?

The MTTF is 3 years and the MTTR is 1 day.

	a.	1096 days
	b.	2000 days
	c.	1 year
	d.	1095 days

3.33 points

QUESTION 25

Multiprocessor network topologies are

	a.	bus, mesh, ring
	b.	SISD, MIMD
	c.	multithread, multicore
	d.	clusters and scale computers

3.33 points

QUESTION 26

Translate unsigned 0xabcdef12 into decimal. The answer is

	a.	235212365
	b.	265423622
	c.	2882400018
	d.	-521233652

3.33 points

QUESTION 27

Assume the following register contents:

$t0=0xAAAAAAAA, $t1= 0x12345678

What is the value of $t2 after the following set of instructions?

Sll $t2,$t0,4

Andi $t2,$t2,-1

	a.	0xAAAAAAA0
	b.	0x0AAAAAAA
	c.	0xBBBBBBBB
	d.	0xBABABABA

3.33 points

QUESTION 28

When processor designer consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are starting with a datapath, where we have I-Mem, Regs, Control, ALU, D-Mem, 2 Add units and 3 Mux units. A single unit of each I-Mem, Add, Mux, ALU Regs, D-Mem, and control blocks have latencies of 400, 100, 30, 120, 200, 350, and 100 ps, respectively and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively.

Consider the addition of a multiplier to the ALU. This addition will add 300 ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction.

What the clock cycle time without this improvement? (consider the critical path only)

	a.	1130 ps
	b.	2000 ps
	c.	1500 ps
	d.	1300 ps

3.33 points

QUESTION 29

What the clock cycle time with this improvement?

	a.	2300 ps
	b.	1430 ps
	c.	1600 ps
	d.	1800 ps

3.33 points

QUESTION 30

What is the new cost with this improvement?

	a.	4600
	b.	5800
	c.	4490
	d.	3360

3.33 points

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