# Description:

# mult $s2, $s3

# When $S2(32-bit) x $S3(32-bit) the result is 64 bits

# MIPS processor places:

# * the most significant 32 bits in Register: Hi

# * the least significant 32 bits in Register: Lo

main:

# Case 1: positive x positive = positive:

addi $s2, $zero,2 # $s2 = 0 + 2 = 2

addi $s3, $zero,3 # $s3 = 0 + 3 = 3

mult $s2, $s3 # (2 points) verify with MARS: Hi = 0x _________ ; Lo = 0x ___________

# Case 2: positive x negative = negative:

addi $s2, $zero,2 # $s2 = 2

addi $s3, $zero,-3 # $s3 = -3 (= ffff fffd) (2's complement)

mult $s2, $s3 # (2 points) verify with MARS: Hi = 0x _________ ; Lo = 0x ___________

# Case 3: negative x negative = positive:

addi $s2, $zero,-2 # $s2 = -2 (= ffff fffe) (2's complement)

addi $s3, $zero,-3 # $s3 = -3 (= ffff fffd) (2's complement)

mult $s2, $s3 # (2 points) verify with MARS: Hi = 0x _________ ; Lo = 0x ___________

wait: j wait # wait