Design a $4-$bit universal decimal counter in VHDL using behavioural modelling, as presented below:

LD $-$ Synchronous Parallel Load

D$3,..,$D$0-$ Parallel Data Inputs

Q$3,...$QQ $-$ Data Outputs

RST $-$ Asynchronous Reset Input

UD $-$ Count direction $($up$/$down$)$

The operation of the universal counter is described by the following function table:

$\backslash$table$[[$RST$,$LD$,$UD$,$Action$],[0,$x$,$x$,$Asynchronous Reset$],[1,0,0,$Count Down$],[1,0,1,$Count Up$],[1,1,$x$,$Synchronous Parallel Load$]]$

Simulate this design with the aid of a 'graphical testbench' $($also known as a "University Program VWF$"$ file$),$ using the Intel Quartus Prime Lite v$23\mathrm{.}1$ software.