Design a $6-$bit, shift$-$right register with D flip flops, and use it to implement a circuit that detects the sequence $"110101"($the rightmost bit is the first arriving$).$

Information shifts one position right when a positive edge of clk occurs. The circuit has the following inputs and outputs $($use exactly these names for inputs and

outputs. Respect upper and lower case$)$:

clk: Input. Clock signal.

RST: Reset signal. When RST $=1$ flip flops are reset to $0.$

IN: Data entry. IN inputs to the leftmost flip flop at each rising edge of clk$.$

OUT: Output. Takes the value $1$ when the last bit of sequence $110101$ is detected $($see example$)$ and returns to $0$ in the next clock cycle.

Note:To properly verify the circuit, VerilUOC$\_$Desktop requires all inputs of the flip flops are connected to some value. So$,$ it is necessary to connect $"$S$"$ inputs to $0$

and "load" inputs to $1.$ To do so$,$ click in "Wiring" $($left menu$),$ select "Constant" and connect the constant $($a logical $1)$ to the "load" inputs. Repeat the process and, in

the Value property of the left menu, replace the $01$ by $00($this will set the constant to $0).$ Connect the resulting constant to the $"S"$ inputs.

Example: