Design a circuit that outputs the following sequence: $\{..\mathrm{.}0,1,2,3,3,0,1,2,3,3,0...\}.$ Each value in the sequence is present for one clock cycle. Strongly consider using an FSM for this design, but use three or less states in that FSM$.$ Minimize the amount of hardware in your design. Design this circuit on the block level using standard digital modules. Don$$t use a ROM, RAM, or decoder in your design; if you use a MUX in your design, don$$t use greater than a $2$:$1$ MUX.