design a combinational hardware that performs the following vector matrix multiplication $($for example, o$1=$ i$1$x$10+$ i$2$x$8+$ i$3$x$4),$ adds the values in the resulting vector $($o $=$ o$1+$o$2+$o$3)$ and outputs the result $($o$).$ i$1,$ i$2,$ i$3$ values are $8-$bit integers in the range $[0-255].[$i$1$ i$2$ i$3]\backslash$times $[1094846427]=[$o$1$ o$2$ o$3]$ in your hardware, you are not allowed to use multiplier hardware for implementing multiplication with a constant. this operation should be implemented using shifter and adder hardware. write a verilog rtl module implementing your hardware. your verilog rtl module should have the following inputs: i$1(8$ bit$),$ i$2(8$ bit$),$ i$3(8$ bit$).$ it should have the following output: o $(16$ bit$).$