Design a common$-$gate JFET amplifier with an input resistance $($Zi$)$ of $50.$ The JFET has the following parameters: $I_{DSS}=6mA,V_P=-3V.$ Assume a supply voltage $($VDD$)$ of $10$ V $.$ Calculate voltage gain Av$,$ gm$,$ ID$,$ VGS$,$ Rs$,$ VDS$,$ RD$,$ Zo$,$ Vi$,$ Vo$,$ rd$,$ gos, gmo and also. create the graph with the load line and find the $Q$ point. Also make a Schematic diagram for the common to gate JFET. Please I am asking that the schmatic diagram gets done and the values inserted on the multisim schmaitic. To calculate all the parameter, values of the most important parametes may be assumed