Design a counter which counts the repeating sequence $010->110->000->011.$

$2.$ Use JK Flip$-$Flops with synchronous active$-$low ClrN and PreN.

$3.$ Simulate the design on ModelSim and verify its correctness.

Design Interface:

Tasks:

$1.$ Design a JK flip$-$flop using behavioral VHDL code.

$2.$ Instantiate several JK flip$-$flops and additional logic and construct the counter circuit.

$3.$ Implement the top$-$level design using a combination of dataflow and structural VHDL modeling.

$4.$ Write a VHDL testbench to simulate and verify the design.