Design a high$-$level state machine that implements a $32-$bit binary multiplier. The system's word size should be $32$ bits. Therefore, the $64-$bit result should be split into high and low word registers. You may not utilize Verilog's built$-$in multiplication operator. Instead, you will implement multiplication as successive addition operations.

$```$

Inputs

clk $[1-$bit$]-$ The system clock

reset $[1-$bit$]-$ Resets the system to its initial conditions

start $[1-$bit$]-$ Begin a multiplication operation on the rising edge

operandA $[32-$bit$]-$ The first binary operand for multiplication

operandB $[32-$bit$]-$ The second binary operand for multiplication

Outputs

finish $[1-$bit$]-$ Indicates when a solution has been obtained

productH $[32-$bits$]-$ The high word of the multiplication result

productL $[32-$bits$]-$ The low word of the multiplication result

$```$

Top Module Format

Submission

You will submit the following on Blackboard:

$1.$ A $.$pdf file containing your high$-$level state diagram.

$2.$ A $.$v file containing your top module.

$3.$ A $.$test.v file containing your testbench module.