Design a Mealy FSM that recognizes a binary input sequence satisfying the followings

$$ It includes odd number of $1$s

$$ It is an odd number when interpreted as a binary number

$$ It is not an all$-$one sequence.

While drawing Next State Logic and Output Logic circuits in the Mealy FSM Schematic, use three

basic gates only $(2-$input AND gates, $2-$input OR gates, NOT gates$).($For the simplicity of the problem,

we assume we may have an arbitrary output for an empty input sequence!$)$

State Transition Diagram

Descriptions of States

State Reduction $($if possible$)$

State Transition & Output Table

State Encoding

State Transition & Output Table with State Codes

K$-$Maps

Simplified Expressions of Next State Bits & Output

Mealy FSM Circuit Schematic

$-$ Next State Logic Circuit

$-$ Output Logic

$-$ Rest of Schematic