Design a memory interface for the $8086,$ which will provide $256$K bytes

of SRAM, organized as $128$K x $16$ bits, starting at address $40000$H and

using SRAM chips $32$K x $8$ bit. The SRAM chipshave three control signals

WR$.$ OE and CS$.$ Use the $74$LS$138(3-$ to$-8$ decoder$)$ for the implementation

of the decoding circuit. The $74$LS$138$ has three control signals G$1,$ G$2$A$,$ and

G$,$B$.$

What is the address space for second chip?

a$.40000$H $-4$FFFFH

Db$.40000$H$-50000$H

c$.40001$H $-4$FFFFH

O d$.40000$H $-4$FFFEH