Design a Power$-$On$-$Reset circuit that guarantees the active$-$high CLR input of a flip$-$flop from the $74$ASXX logic family will result in a valid logic HIGH applied to it for $1s$ after the system power is applied in order that the flip$-$flop initializes into $Q=0.$ Provide a circuit diagram, values for R and C $,$ the equation that describes the waveform and a plot showing both the waveform and the logic level involved. See below for a graphic on which to draw your plot.

equation :

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