Question: Design a Verilog HDL for a combinational circuit with three inputs, X , Y , and Z , and three outputs, A , B ,

Design a Verilog HDL for a combinational circuit with three inputs, X, Y, and Z, and three
outputs, A, B, and C. When the binary input is 0,1,2, or 3, the binary output is one greater
than the input and when the binary input is 4,5,6, or 7, the binary output is one less than
the input. Also write stimulus that the Verilog model provides the correct output

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