Design a Verilog module that will implement the Shift$-$and$-$Subtract division

algorithm for unsigned integers.

The algorithm will perform the following function $Y$:UlarrU$\frac{V}{x},$ where

registers $U,V$ will initially contain the dividend and $x$ will contain the

divisor. Upon the completion of the algorithm, $Y$ will store the quotient

of the result and U the remainder of the result. Implement U$,$ V$,$ X$,$ Y

as $4-$bit registers.

Note that the implementation must follow the Shift$-$and$-$Subtract RTL

code from our lectures, do not attempt to implement the division via the

$"/"$ Verilog operator. Use the DE$-2$ switches to enter the input values

and instances of the $7-$segment decoder Verilog module from Lab $2$ to

display the result after the division.