Design a watchdog timer that takes a clock (with a clock frequency 4 KHz) and a reset pin as its input as two signals S1 and S2 as its output. S1 goes high when the timer reaches 25 msec to alert the user that the process may be long. S2 goes high when the timer exceeds 30 msec. When S2 is high, the system resets immediately the process is at fault). Use counters and logic gates for your design. Also assume that under normal operation a processor resets the timer every 20 msec.