Design an I$/$O system for the $8085$ microprocessor with the following characteristics:

An input peripheral$-$mapped port with address $42H.$

An output memory$-$mapped port with address $43xH($x means don't care$).$

Assume that the device selection input for both ports is active low.

You are limited to the following chips $($Max$)$:

$\backslash$table$[[$Chip type,Count$],[3$:$8$ Decoder,$1],[$Octal Latch gate,$1],[$Octal D$-$Flip$-$Flop,$1],[4-$inputs NAND gate,$5],[4-$inputs OR gate,$3],[$Inverter gate,$6]]$