Design and implement a 4-bit up counter with parallel load using the up-counter of the finite-state machine you built above with the following inputs and outputs: CLR for the active-low clear to set the counter to all 0. G for the input to change the counter value at the rising edge of clock cycle Dz-, for the parallel load data input LD to control the parallel data load. When LD = 1, the counter receives the parallel data from D3, at the rising edge of G. When LD = 0, the counter value is incremented at the rising edge of G. 0 03-4 to output the 4-bit value of the counter You need to use the quadruple 2-to-1 multiplexer you built in the previous lab. Build a circuit to test and verify that you counter functions correctly. Run a simulation to show both the function and the delay of its value change of your counter Package your counter into a device named "UCT4". You will use this device when you build your computer in the next few labs. Design and implement a 4-bit up counter with parallel load using the up-counter of the finite-state machine you built above with the following inputs and outputs: CLR for the active-low clear to set the counter to all 0. G for the input to change the counter value at the rising edge of clock cycle Dz-, for the parallel load data input LD to control the parallel data load. When LD = 1, the counter receives the parallel data from D3, at the rising edge of G. When LD = 0, the counter value is incremented at the rising edge of G. 0 03-4 to output the 4-bit value of the counter You need to use the quadruple 2-to-1 multiplexer you built in the previous lab. Build a circuit to test and verify that you counter functions correctly. Run a simulation to show both the function and the delay of its value change of your counter Package your counter into a device named "UCT4". You will use this device when you build your computer in the next few labs