Design $($i$.$e$.$ specifications $$ algorithm $$ DP $$ ASM Chart$)$ a

configurable UART $($that reads data serially and output it in

parallel$).$ Input data are $7-$bits $+$ a parity bit. The input is normally

high $($i$.$e$.$ logic $1$ value$)$ when it is idle. When there is data, the input

is first lowered to $0$ for two or three cycles $($called start bits$),$ then

$8-$bits of data $(7-$bits $+$ parity$)$ would follow. If there is another flit of data, a continuation bit $($Logic $0)$

is received followed by another $8-$bits of data and so on$.$ If a $1$ is received after a flit that means no

more data $($stop bit$).$ The first flit received after a reset represents the configuration data; the number

of start bits $(2$ or $3)$ and the type of parity used $(0$ for even parity and $1$ for ODD parity$).$ Every time $8-$

bits are received, the $7-$bit data outputted $($if the parity bit is correct$)$ along with a strb signal. If the

parity is wrong, an error status output is set high.