design in Verilog a decoder

input is a binary number 5 a

output is a bit pattern 22 bits wide that contains exactly one 1

bit 0 of the output is the least significant bit

that is:

* a z

* 0 -> 0000000000000000000001

* 1 -> 0000000000000000000010

* 2 -> 0000000000000000000100

format:

module decode22

#( bW = 5, aW = 22 )

(

input logic [bW-1:0] a,

output logic [aW-1:0] z

);

[insert code here]

endmodule

~