Design Problem

A Mealy sequential circuit accepts $2-$bit input $x$ and generates $3-$bit output $Z.$ The output $Z$ represent a binary number whose value equals to the accumulated total number of $1\text{'}$s received at the inputs. The circuit resets every three clock pulses. Implement the state table

Example:

$\backslash$table$[[,$X $1$ X $0,1,1,1,1,0,1,1,1,0,1,1,11],[$N$=$ No$.$ of $1\text{'}$s$,2,3,5,1,1,2,1,3,3,2,4,6],[,$Z$2$ Z$1$ Z$0,0,1,101,001,0,1,001,011,011,010,0,11]]$